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■研究成果及著作■
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| 【期刊論文】 |
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研討會論文 |
專書、技術報告等 | |
| [1]. |
Jyh-Ming Huang and Ted C. Yang, “Path-Based Routing Schemes
for Multicast Communication,” submitted to International
Journal of Information Processing Letters |
| [2]. |
Che-Wun Chiou and Ted C. Yang, “Majority-voting Approach
for Common-multiplicand Multiplication Algorithm,” The Journal
of Ching-Ying Institute of Technology, Vol. 22, No. 2, 2002,
pp.53-56 |
| [3]. |
Jyh-Ming Huang and Ted C. Yang, “Fault Tolerant Multi
destination Multicast Based on Hierarchical Block Ring,” The
International Journal of Parallel and Distributed Systems and
Networks, vol. 5, no. 3, 2002, pp.89-97 |
| [4]. |
L. Wang and Ted C. Yang, “On the Boosting of Instruction
Scheduling by Renaming, ” The Journal of Supercomputing,
Vol. 19, No. 2, June 2001, pp. 173-197 |
| [5]. |
J. M. Huang and Ted C. Yang, “Multidimensional Fault
Tolerance in Cube-Connected Cycles Architecture,” International
Journal of Computers and Applications, Vol.22, No.3, Sept. 2000,
pp. 140-150 |
| [6]. |
L. Wang and Ted C. Yang, “A Compiler-Based Speculative
Execution Scheme for ILP Enhancement,“ Journal of Information
Science and Engineering, Vol. 16, No. 1, Jan. 2000, pp. 1-12 |
| [7]. |
L. Wang and Ted C. Yang, “Compiler/Hardware Co-design
for Instruction Boosting in ILP Processors,“ IEE Proceedings-Computers
and Digital Techniques, Vol. 146, No. 6, Nov. 1999, pp. 269-274 |
| [8]. |
C.W. Chiou and Ted. C. Yang, “Parallel Modular Multiplication
with Table Look-Up,“ International Journal of Computer Mathematics,
Vol.69, 1998, pp.49-55 |
| [9]. |
楊濬中,
王壘,
"極長指令集處理機設計原理概述,"
電子月刊,
六月號,
第35期,
1998, pp. 72-75. |
| [10]. |
Jyh-Ming Huang, Chung-Liang Yen, Chia-Cheng Liu, and Ted
C. Yang, “A Novel Broadcast Approach for Multi-Port Wormhole
Torus Networks,” Information Engineering, vol.34, Feng Chia
University, 1998, pp. 36-47 |
| [11]. |
C. W. Chiou, and Ted C. Yang, “Self-Purging Redundancy
with Adjustable Threshold for Tolerating Multiple Module Failures,”
IEE Electronic Letters, Vol. 31, No. 11, 1995, pp. 930-931 |
| [12]. |
C. W. Chiou and Ted C. Yang, "Iterative Modular
Multiplication Algorithm Without Magnitude Comparison,"
IEE Electronic Letters, Vol.30, No. 24, 1994, pp. 2017-2018 |
| [13]. |
C. W. Chiou and Ted C. Yang, "A Division
Algorithm Without Number Comparison," International
Journal Computer Mathematics, Vol. 54, 1994, pp. 53-56 (SCI) |
| [14]. |
H. Y. Lo and Ted C. Yang, "Balanced High-Speed Residue
Number VLSI Multiplier with Error Detection," IEE Proceedings,Vol.l38,
No. 3, 1991, pp. 421-423 (SCI) |
| [15]. |
Ted C. Yang
and C. W. Chiou, "Random Pattern Testability Based on Critical
Path Tracing," International Journal of Computer Applications
in Technology, U.K., Vol.3, No. 2, 1990, pp. 88-91 (EI) |
| [16]. |
Ted C. Yang
and C. W. Chiou, "Testable PLA Design with Minimal Overhead,"
Integration, the VLSI Journal, The Netherlands, Vol. 10,
1990, pp. 9-18 (EI) |
| [17]. |
Ted C. Yang
and C. W. Chiou, "Universal Syndrome-Testable Design of
Programmable Logic Arrays," Integration, the VLSI Journal,
The Netherlands Vol. 10, 1990, pp. 3-8 (EI) |
| [18]. |
Ted C. Yang,
C. W. Chiou, and J. M. Lin, "On the Fast Generation of
Base-K Logarithm," International Journal of Computer
Mathematics, U.K., Vol.30, 1989, pp. 133-141 (EI) |
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| 【
研討會論文】 |
| [1]. |
Jyh-Ming Huang, Chua-Huang
Huang, and Ted C. Yang, “Tensor Product Modeling of Fault
Tolerant Multiprocessor Architectures,” Proceedings of The
2002 International Conference on Parallel and Distributed Systems,
Dec. 17-20, 2002, pp. 495-500, NCU, Chung-Li, Taiwan |
| [2]. |
Jyh-Ming Huang and Ted C. Yang, “Multidestination Multicast
Communication Based on Hierarchical Block Rings,” Proceedings
of The ISCA 14th International Conference on Parallel and Distributed
Computing Systems, Aug. 2001, pp. 31-36, Richardson, Texas USA. |
| [3]. |
Jyh-Ming Huang and Ted C. Yang, “A Hierarchical Block-Ring
Based Multicast Communication Scheme,” Proceedings of The
2001 International Conference on Parallel and Distributed Techniques
and Applications, June 2001, pp. 305-311, Las Vegas, Nevada,
USA. |
| [4]. |
L. Wang and Ted C. Yang, "A Theoretical Analysis
for Instruction Boosting in ILP Processors," The 2001
International
Symposium on Information Systems and Engineering (ISE'2001),
USA, June 2001, pp.121-128. |
| [5]. |
Jyh-Ming Huang and Ted C. Yang, “A Dynamic Fault-Tolerant
Mesh Architecture, “ Workshop on Parallel and Distributed
Real-Time Systems, San Juan, Puerto Rico, April 1999, pp. 418-424 |
| [6]. |
Ted C. Yang
and L. Wang, “On the Design and Modeling of a Homogeneous VLIW
Architecture,” Proceedings of International Conference on
Computer Architecture, ICS, Dec. 1996, pp. 82-89 |
| [7]. |
Ted C. Yang,
Kae-Fen Hwang, Jiunn-Wen Jou, and Chia-Cheng Liu, “An SCSI-Based
Adaptive Router in Torus Network,” Proceedings of International
Conference on Computer Architecture, ICS, Dec. 1996, pp. 241-252 |
| [8]. |
L. Wang, J. W. Jou, H. Y. Hsu, and Ted C. Yang, “A Dual-Mode
Homogeneous VLIW Computer and Its System Features,” Proceedings
of the Workshop on CPU Research and Development, May 1995, National
Chiao-Tung Univ., pp.65-72 |
| [9]. |
C. R. Huang, J. W. Jou, L. Wang, and Ted C. Yang, “On
Performance Evaluation of Shift Scheduling and HVLIW Architecture,“
Proceedings of the first Workshop on Compiler Techniques
for High-Performance Computing, Feb. 1995, National Central
Univ., pp.110-116 |
| [10]. |
L. Wang and Ted C. Yang, "On the Design and Modeling
of a Homogeneous VLIW Architecture," Proceedings International
Conference on Computer Architecture, ICS, Dec. 1996, pp. 82-89 |
| [11]. |
Kae-Fen Hwang, Jiunn-Wen Jou, Chia-Cheng Liu, and Ted C.
Yang, "An SCSI-Based Adaptive Router in Torus Network,"
Proceedings International Conference on Computer Architecture,
ICS, Dec. 1996, pp. 241-252 |
| [12]. |
L. Wang, J. W. Jou, H. Y. Hsu, and Ted C. Yang, "A
Dual-Mode Homogeneous VLIW Computer and Its System Features,"
Proceedings of the Workshop on CPU Research and Development,
May 1995, National Chiao-Tung Univ., pp.65-72 |
| [13]. |
C. R. Huang, J. W. Jou, L. Wang, and Ted C. Yang, "On
Performance Evaluation of Shift Scheduling and HVLIW Architecture,"
Proceedings of the first Workshop on Compiler Techniques
for High-Performance Computing, Feb. 1995, National Central
Univ., pp. 1 10-1 16 |
| [14]. |
J. Y. Yu, Kuo-Kuei Lin, and Ted C. Yang,"On Shift
Scheduling of Homogeneous VLIW Architectures," Proceedings
of the International Computer Symposium, Dec. 1992, PP.705-712 |
| [15]. |
W. C. Tseng, L. Wang, H. Y. Hsu, and Ted C. Yang, "The
Design of Asymmetrical Register Structure for VLIW/FC,"
Proceedings of the International Computer Symposium, Dec.
1992, pp. 143-149 |
| [16]. |
C. P. Lin, Y. Huang, and Ted C. Yang, "Interconnection
Networks for a Homogeneous Very Long Instruction Word Architecture,"
Proceedings of the International Computer Symposium, Dec.
1992, pp. 824-830 |
| [17]. |
C. W. Chiou, H. C. Wu, and Ted C. Yang, "Random
Testing of a RISC-Type Processor,” Proceedings of the ISMM
International Symposium on Computer Applications in Design,
Simulation, and Analysis, New Orleans, LA., USA, 1990, pp. 90-93 |
| [18]. |
C. C. Chang, G. G. Lin, H. Y. Hsu, H. C. Wu, and Ted C. Yang,
"RISC/B Virtual Memory Management and Cache Design,"
Proceedings of the ISMM International Symposium on Computer
Applications in Design, Simulation, and Analysis, New Orleans,
LA., USA, 1990 |
| [19]. |
C. W. Chiou and Ted C. Yang, "Fully Testable PLA
Design with Minimal Extra Input," Proceedings of the
European Design Automation Conference on Systems Integration,
Glasgow, Scotland, 1990, pp. 633-638 |
| [20]. |
Y. Y. Chen and Ted C. Yang, "Modeling and Performance
Evaluation of RISC/B Processor," Proceedings of the
First International Conference on Systems Integration,
Morristown, NJ., USA, 1990, pp. 1-11 |
| [21]. |
C. T. Hwang, W. B. Tsay, C. H. Chang, A. C. Liu, and Ted
C. Yang, "Error Recovery and Data Consistency in a
Fault-Tolerant Distributed System," 1989 ISMM International
Conference on Intelligent Distributed Processing, Fort Lauderdalem,
USA, pp. 45-48 |
| [22]. |
K. C. Chem, H. Y. Hsu, K. K. Lin, Y. Huang, and Ted C. Yang,
"Design Tradeoff in RISC/B Processor," Proceedings
of the 1989 International Computer Conference, 1989, pp. 10-14 |
| [23]. |
H. J. Wang, H. Y. Hsu, K. K. Lin, and Ted C. Yang, "Multi-Coprocessor
Parallel Architecture for RISC/B," Proceedings of the
1989 National Computer Conference, 1989, pp. 154-163 |
| [24]. |
Y. Y. Chem, K. C. Chem, and Ted C. Yang, "Performance
Analysis of RISC/B Processor," Proceedings of the 1988
International Computer Symposium, 1988, pp. 215-220 |
| [25]. |
S. W. Tai, Y. S. Lee, and Ted C. Yang, "Optimizing
Delayed Loads and Delayed Branches for RISC/B," Proceedings
of the 1988 International Computer Symposium, 1988, pp. 182-187 |
| [26]. |
Y. Hwang, K. C. Chem, and Ted C. Yang, "Design Decisions
on RISC/B Execution Strategy," Proceedings of the 1988
ISMM International Conference on Mini and Microcomputers, 1988,
pp. 6-10 |
| [27]. |
H. Y. Hsu, S. C.Chen, K. C.Chen, C. T.Chen, and Ted C. Yang,
"On the Design of RJSC/B Instruction Pipeline," Proceedings
of the 1987 National Computer Symposium, 1987, pp. 66-75 |
| [28]. |
J. C. Chen, K. K. Lin, H. Y. Hsu, and Ted C. Yang, "The
Design and Implementation of an Event-Driven Logic Simulator,"
Proceedings of the 1987 National Computer Symposium, 1987,
pp. 538-544 |
| [29]. |
C. W. Chiou and Ted C. Yang, "A General Reconfigurable
Redundancy System,” Proceedings of the 1987 International
Phoenix Conference on Computers and Communications, 1987, pp.
84-88 |
| [30]. |
Ted C. Yang
and C. W. Chiou, "Syndrome Testable Design with Minimal
Input Insertion for Multiple Faults," Proceedings of
the 1987 International Phoenix Conference on Computers and Communications,
1987, pp. 100-104 |
| [31]. |
H. Y. Hsu, Y. Hwang, K. C. Chem, C. T. Chem, and Ted C. Yang,
"Control Path and Data Path Design for RISC/B," Proceedings
of the 1987 National Computer Symposium, 1987, pp. 57-65 |
| [32]. |
S. W. Tai, K. K. Lin, and Ted C. Yang, "Code Reorganization
and Register Allocation under the RISC Pipeline Environment,"
Proceedings of the 1987 National Computer Symposium, 1987,
pp. 47-56 |
| [33]. |
Ted C. Yang
and C. W. Chiou, "Design of Self-Checking PLAs Using Alternating
Logic," Proceedings of the 1987 International Test Conference,
1987, pp. 189-196 |
| [34]. |
Ted C. Yang
and C. W. Chiou, "A State-Based Testability Measure for
Digital Circuits," Proceedings of the International
Computer Symposium, 1986, pp. 174-179 |
| [35]. |
H. Y. Hsu, Y. Hwang and Ted C. Yang, "The Sharing
of Register File in RISC Architectures," Proceedings
of the International Computer Symposium, 1986, pp 288-297 |
| [36]. |
S. R. Tsai and Ted C. Yang, "A Dynamic Job Scheduler
for distributed Multiaccess Networks," Proceedings of
the International Computer symposium, 1986, pp. 1573-1582 |
| [37]. |
Ted C. Yang
and O. F. Chen, "Reliability Modeling and Analysis of a
Generalized Responsive Redundancy Scheme,"
Proceedings of the IEEE International Conference on Computer
Design: VLSI in Computers, 1985, pp. 514-517 |
| [38]. |
S. R. Tsai and Ted C. Yang, "A Study on Load Balancing
of Distributed Computer Systems," Proceedings of the
National Computer Symposium, 1985, pp. 59-69 |
| [39]. |
Paul C. P. Lin and Ted C. Yang, "A Microcomputer
Based Control System for an Intelligent Robot," Proceedings
of the National Computer Symposium, 1985, pp.1552-1565 |
| [40]. |
S. S. Hong and Ted C. Yang, "Reliability and Availability
Estimation of a Reliable Microprocessor-Based System,"
Proceedings of the National Computer Symposium, 1985, pp.300-307 |
| [41]. |
S. M. Guo and Ted C. Yang, "Software Implemented
Personal Computer Network," Proceedings of the National
Computer Symposium, 1985, pp. 944-951 |
| [42]. |
Ted C. Yang
and O. F. Chen, "Reliability Modeling and Analysis of a
Two-Dimensional Redundancy Scheme," Proceedings of the
4th Hungarian Computer Science Conference, 1985,
Hungary |
| [43]. |
C. W. Chiou and Ted C. Yang, "On-line Error Detection
in VLSI-Implemented Interconnection Network," Proceedings
of the National Computer Symposium, 1985, pp.875-887 |
| [44]. |
Ted C. Yang
and J. Liu, "A Reliable Multi-Microprocessor System,"
Proceedings of the 1984 International Conference on Industrial
Electronics Control and Instrumentation, 1984,
Japan Tokyo, pp. 1169-1176 |
| [45]. |
S. S. Horng and Ted C. Yang, "A Reliable Microprocessor-Based
Traffic Controller," Proceedings of the International
Computer Symposium, 1984, pp.1472-1481 |
| [46]. |
K. K. Chow, W. B. Leonard and Ted C. Yang, "A Wavelength
Division Multiplexed(WDM) Optical Data Bus for Future Military,”
Proceedings of the AIAA/IEEE 6th Digital Avionics System
Conference, 1984, 399-404 |
| [47]. |
Ted C. Yang
and A. S. Wojcik, "A Study of Reduced Dependence In Multi-valued
Sequential Machines," Proceedings of the 13th International
Symposium on MVL, 1983, pp. 12-20 (EI) |
| [48]. |
Ted C. Yang,
"A Microprocessor-Based Fault Tolerant Traffic Controller,”(
In Chinese )," 1983 Symposium on Automatic Control Proceedings,
1983 |
| [49]. |
Ted C. Yang,
"L-rep:A Reliability Estimation Program," Proceedings
of the 4th Digital Avionics System Conference, 1981 |
| [50]. |
Ted C. Yang
and A. S. Wojcik, "Parallel and Serial Decompositions of
Multi-valued Sequential Machines," Proceedings of the
8th International Symposium on Multi-valued Logic, 1978, pp-179-186
(EI) |
| [51]. |
Ted C. Yang,
"A gate-Level Logic Simulator for 3-Valued Switching Networks,"
Proceedings of the 7th International Symposium on MVL, 1977,
pp. 47-50 (EI) |
| [52]. |
Ted C. Yang
and A. S. Wojcik, "A Minimization Algorithm for Ternary
Switching Functions," Proceedings of the 6th International
Symposium on Multi_Valued Logic, 1976, pp. 241-255 (EI) |
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專書、技術報告等】 |
| [1]. |
Ted C. Yang,
"Path and Testability Design for RISC/B," Information
Engineering, No. 24,
Feng Chia University, 1988 |
| [2]. |
Ted C. Yang,
"Implementating and Test Report ofRISC/B Prototype,"
Information Engineering, No. 24,
Feng Chia University, 1988 |
| [3]. |
Ted C. Yang,
"Modeling and Preliminary Performance Evaluation of RISC/B,"
Information Engineering, No. 24, Feng Chia University,
1988 |
| [4]. |
Ted C. Yang,
"Consistency and Capability Checking of MMU/Cache in RISC/B,"
Information Engineering, No.24,
Feng Chia University, 1988 |
| [5].
|
Ted C. Yang,
"Experience in ISPS Simulation on RISC Architecture,"
Information Engineering, No. 23,
Feng Chia University, 1987 |
| [6].
|
Ted C. Yang,
"A dBASE III - Based Business Cards System," ( In
Chinese ), Information Engineering, No. 23,
Feng Chia University, 1987 |
| [7].
|
Ted C. Yang,
"Multiple Windows Register File for Multiple Tasks,"
Information Engineering, No. 23,
Feng Chia University, 1987 |
| [8]. |
Ted C. Yang,
"Design and Implementation of Dynamic Process Scheduler
for Multiprocessor System," Information Engineering,
No. 22,
Feng Chia University, 1986 |
| [9]. |
Ted C. Yang,
"A Reliable Multi-Microprocessor System," Information
Engineering, No. 21,
Feng Chia University, 1985 |
| [10]. |
Ted C. Yang,
"An Optically Linked Distributed Computer System,"
Information Engineering, No.. 20,
Feng Chia University, 1984 |
| [11]. |
Ted C. Yang,
"A Design of Interconnect Computer Network," Information
Engineering, No. 19,
Feng Chia University, 1983 |
| [12]. |
Ted C. Yang,
"Interconnect Technology," LMSC-D086353 Lockheed
Missiles and Space Company, 1981,
Palo Alto, USA |
| [13]. |
Ted C. Yang,
"Fault-Tolerant Spaceborne Computer Requirements,"
LMSC-L041791, Lockheed Missiles and Space Company, 1980,
Palo Alto, USA. |
| [14]. |
Ted C. Yang,
"The Decomposition of Multiple-Valued Sequential Machines,"
Technical Report, Computer Science Department, Illinois
Institute of Technology,
Chicago, 1977 |
| [15]. |
Ted C. Yang,
"A Study Report of the IMS/360," Technical Report
76-2, CS Department, Illinois Institute of Technology,
Chicago, 1976 |
| [16]. |
Ted C. Yang,
"12860-An Interface Makes an INTERDATA/4 look like an IBM
360/67 Selector Channel," MS. Thesis, CS Department,
Washington State University, 1971, Pullman, Washington |
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