• 期刊論文(18)

    [1] A low voltage and low power flip-flop design using virtual VDD scheme
    Jin-Fa Lin , Shao-Wei Yu, Chang-Ming Tsai & Ming-Hwa Sheu
    Journal of Semiconductor Technology and Science
    (Accepted).

    [2] Low complexity and low power sense-amplifier based flip-flop design
    Po-Yu Kuo , Chia-Hsin Hsieh, Jin-Fa Lin Ming-Hwa Sheu& Yi-Ting Hung
    IEICE Trans. Electron
    (Revised).

    [3] A novel low power flip-flop design using footless scheme
    Jin-Fa Lin , Ming-Yan Tsai, Ching-Sheng Chang & Yu-Ming Tsai
    Analog Integrated Circuits and Signal Processing, vol.97 pp.365-370
    Nov. 2018. (SCI).

    [4] A modified static contention free single phase clocked flip-flop design for low power applications
    Jin-Fa Lin and Ming-Yin Tsai
    Journal of Semiconductor Technology and Science,vol.18
    Oct. 2018. (SCI).

    [5] Low-power 19-Transistor true single-phase clocking flip-flop design based on logic structure reduction schemes
    Jin-Fa Lin, et.al
    IEEE Transactions on VLSI, vol.25, pp. 3033-3044
    Nov. 2017. (SCI).

    [6] Low-power latch adder based multiplier design
    Jin-Fa Lin, et.al
    Journal of Semiconductor Technology and Science, vol.17, pp. 806-814
    Dec. 2017. (SCI).

    [7] Low power divider design using pass transistor logic circuit schemes
    Jin-Fa Lin, et.al
    ICIC Express Letter, pp.1547-1552
    July 2016. (EI)

    [8] Low power SR-latch based flip-flop design using 21 transistors
    Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-Shiang Cheng
    Journal of Low Power Electronics,vol.12, pp.112-116
    Jun. 2016.(E-SCI)

    [9]Single-ended structure sense-amplifier-based flip-flop for low power systems
    Jin-Fa Lin, et.al
    IEE Electronic Letter, vol.51, pp.20-21
    Jan. 2015. (SCI)

    [10] A low power pulse triggered flip-flop design based on a signal feed through scheme
    Jin-Fa Lin
    IEEE Transactions on VLSI, vol.20, pp.181-185
    Jan. 2014. (SCI)

    [11]Low voltage and low power divide-by-2/3 counter design using pass transistor logic circuit technique
    Yin-Tsung Hwang and Jin-Fa Lin
    IEEE Transactions on VLSI, vol.20, pp.1738-1742
    Sep. 2012. (SCI)

    [12] Low power pulse-triggered flip-flop design with conditional pulse enhancement scheme Yin-Tsung Hwang, Jin-Fa Lin and Ming-Hwa Sheu
     IEEE Transactions on VLSI, vol.20, pp.361-366
    Feb. 2012. (SCI)

    [13] Low power pulse-triggered flip-flop design using gated pull-up control scheme
    Jin-Fa Lin
    IET Electronic Letter, vol.47, pp.1313-1314
    Nov. 2011. (SCI)

    [14]A low complexity dual-mode pulse-triggered flip-flop design based on unified AND/XNOR logic
    Jin-Fa Lin, Yin-Tsung Hwang and Ming-Hwa Sheu
     IEICE Transaction on Fundamentals, vol. E-93-A, no.12, pp.2755-2757
    Dec, 2010. (SCI)

    [15]Low power pulse generator design using hybrid logic
    Jin-Fa Lin, Yin-Tsung Hwang and Ming-Hwa Sheu
     IEICE Transaction on Fundamentals, vol. E-93-A, no.6, pp.1266-1268
    June, 2010. (SCI)

    [16] A low complexity low power single transition detector design for self-timed circuits
    Jin-Fa Lin, Yin-Tsung Hwang and Ming-Hwa Sheu
     IEICE Transaction on Fundamentals, vol. E-93-A, no.4, pp. 843-845
    Apr, 2010. (SCI)

    [17]Novel low complexity dual mode pulse generator designs
    Jin-Fa Lin, Yin-Tsung Hwang and Ming-Hwa Sheu
     IEICE Transaction on Fundamentals, vol. E-91-A, pp.1812- 1815
    July, 2008. (SCI)

    [18]A novel high speed and energy efficient 10-transistor full adder design
    Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu and Cheng-Che Ho
    IEEE Transactions on Circuits and Systems I, vol.54, pp.1050-1059
    May. 2007. (SCI)

     



    會議論文(11)

    [1]Jin-Fa Lin, Ching-Sheng Chang, Wei-Jun Chien, Chang-En Cai, Qiu-Bo Yao, “Development of insect-trapping system implemented”, AIT, Apr. 2017.

    [2]Jin-Fa Lin, Ming-Yin Tsai, Chia-Hsuan Chen, Chiao-Lan Ku and Yu-Wei Chang, “A 19-transistor flip-flop design using pass transistor circuit scheme with 81% energy saving”, VLSICAD, Aug. 2015.

    [3]林進發,蔣云容,鄭宇翔,李崑生, “具低複雜度與低功率消耗特性之正反器設計”, 2015民生電子研討會.

    [4]洪顗婷,翁晨軒,許明華,林進發 “具有低功率與高效能之感測放大正反器設計與晶片實現”, 2015 Conference on Intelligent Electronics Designs and Applications, Nov. 2015.

    [5] Jin-Fa Lin , Yu-Cheng Li, Yu-Wei Chang, Ming-Yen Tsai, Ciao-Lan Gu, “Low voltage and high performance divide-by-2 design using pseudo nMOS circuit scheme”, the 9th International Conference on Advanced Information Technologies/ Consumer Electronics Forum (AIT/CEF 2015), Apr. 2015.

    [6] Dong-Ting Hu, Jin-Fa Lin, Chen-Syuan Wong, Jui-Yang Liao and Chia-Ching Chen, ”Low Power Counter Design Using Wired Logic Circuit Technique”, Apr. 2013.

    [7] Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, “Low power 10-transistor full adder design based on degenerate pass transistor logic”, IEEE International Symposium on Circuits and Systems (ISCAS), May 2012.

    [8] Jin-Fa Lin , Jui-Yang Liao, Dong-Ting Hu, Hung-Chi Chu, “A novel low power XNOR gate using symmetrical circuit technique for ultra low voltage applications”,  International Conference on Advanced Information Technologies (AIT 2012).

    [9]Jin-Fa Lin, Ming-Hwa Sheu, Peng-Siang Wang, “Pulse-triggered flip-flop design with PTL style control scheme, IEEE Region 10 Conference, Nov. 2011

    [10]林進發,陳韋谷,李育晟, “防止車門開啟意外之警示系統”, 2014 AIT Conference, Apr. 2014.

    [11]林進發,林文昌,葉威志,洪紳寶,李育晟, “適用於次臨界區操作之對稱式NAND閘”, 2014 AIT Conference, Apr. 2014.